1. Field of the Invention
This invention relates generally to the data processing apparatus and, more particularly, to the specialized high performance processors generally referred to as digital signal processing units. This invention relates specifically to the reduction of energy in digital signal processing units that have a plurality of digital signal processors, the digital signal processors having the further property that signal groups can directly exchanged therebetween.
2. Background of the Invention
As the need for increasing computation power has been recognized, part of the response to this need has been the incorporation of more than one digital signal processors in a digital signal processing unit. Referring to FIG. 1, a digital signal processing unit 1 having two digital signal processors, according to the prior art, is shown. A first digital signal processor 10 includes a core processing unit 12 (frequently referred to as a processing core), a direct memory access unit 14, a memory unit or memory units 16, and a serial port or serial ports 18. The memory unit 16 stores the signal groups that are to be processed or that assist in the processing of the signal groups to be processed by the core processing unit 12. The core processing unit 12 performs the bulk of the processing of signal groups in the memory unit. The direct memory access unit 14 is coupled to the core processing unit 12 and to memory unit 16 and mediates the signal group exchange therebetween. The serial port 18 exchanges signal groups with components external to the digital signal processing unit 1. The core processing unit 12 is coupled to the serial port 18 and to the memory unit 16 and controls the exchange of signal groups between these components. FIG. 1 also includes a second digital signal processor 10xe2x80x2. The second digital signal processor 10xe2x80x2 is a replica of the first digital signal processor 10 and includes a core processing unit 12xe2x80x2, a direct memory access unit 14xe2x80x2, a memory unit 16xe2x80x2, and a serial port 18xe2x80x2. The functionality and inter-relationships of the components of the digital signal processors 10 and 10xe2x80x2 is the same.
The digital signal processor is typically designed and implemented to have limited functionality, but functions that must be repeated and performed rapidly. The fast fourier transform (FFT) calculation and the Viterbi algorithm decoding are two examples where digital signal processors have been utilized with great advantage. To insure that the digital signal processors operate with high efficiency, the core processing is generally optimized for the performance of the limited functionality. Part of the optimization process involves the off-loading, to the extent possible, any processing not directed toward the optimized function. Similarly, the exchange of signal groups involving the core processing unit and the memory unit has been assigned to the direct memory access controller.
In addition, many of the applications for which the digital signal processing units are the best candidates are also applications in which low power consumption is of high importance, e.g. cell phones, pagers, etc. However, for a variety of reasons such as the increased computational load, the inclusion of plurality of digital signal processors in a single digital signal processing unit has become increasingly important. As will be clear, the inclusion of a plurality of digital signal processors in a single digital signal processing unit has the effect of increasing the power consumption of the unit.
In the past, portions of the digital signal processor could be placed in an IDLE mode. In this mode of operation, the clock signal is removed from all or part of the digital signal processor. Because in the absence of a clock signal, the apparatus remains in a low energy mode until the clock signal is reapplied.
Referring to FIG. 2A, the block diagram of a digital signal processors 10, 10xe2x80x2 capable of implementing an IDLE mode of operation, according to the prior art, is shown. The core processing unit 12, 12xe2x80x2, the direct memory access controller 14, 14xe2x80x2, the memory unit 16, 16xe2x80x2 and the serial port 18, 18xe2x80x2, have the same relationship in the digital signal processor 10, 10xe2x80x2 as in FIG. 1. In addition, an external clock signal is applied to a clock buffer unit 21, 21xe2x80x2. The clock buffer unit can include a phase-locked loop (not shown). A clock signal from the clock buffer unit 21, 21xe2x80x2 is applied to the core processing unit 12, 12xe2x80x2. In particular, the clock signal is applied to a clock control unit 121, 121xe2x80x2 of the core processing unit 12, 12xe2x80x2. From the clock control units 121, 121xe2x80x2, a clock signal is transmitted to the direct memory access controller 14, 14xe2x80x2 and to the serial port.18, 18xe2x80x2. From the direct memory access controller 14, 14xe2x80x2, the clock signals are distributed to the memory unit 16, 16xe2x80x2. (Note the distribution of clock signals described here is meant to be illustrative. Other systems of the distribution of clock signals will be clear to those familiar with digital signal processors.) As will be clear to those skilled in the art, the presence of clock signals is necessary for the operation of the digital signal processor and each of components thereof. In the absence of clock signal, the apparatus of the digital signal processor remains in IDLE state, a state of the processing apparatus that consumes a reduced amount of power in the absence of clock signals. It is desirable feature of digital signal processing units for certain application that the processing apparatus be in the IDLE mode when ever the signal groups are not being manipulated.
Referring next to FIG. 2B, the operation of the clock controller unit 121 of the core processing unit 12 is illustrated. The clock signal from the clock buffer unit 21 is applied to a first input terminal of logic AND gate 124 and to a first input terminal of logic AND gate 125. A second input terminal of logic AND gate 124 is coupled to an output terminal of latch unit 122, while the second input of logic AND gate 125 is coupled to an output terminal of latch unit 123. The latch units 122 and 123 receive external control signals on first input terminals. The external control signals set and maintain a positive logic signal at the output of the latch units 122 and 123. An IDLE signal 0 and IDLE signal 1 are applied to the second input terminals of latch unit 122 and latch unit 123, respectively. The IDLE signal 0 and the IDLE signal 1 remove the positive latch signal from the output terminals of the latch units to which they are applied. The operation of the clock control unit 121 can be understood as follows. When the latch units 122 and 123 are set, a positive logic signal is applied to an input terminal of logic AND gate 124 and the input terminal of logic AND gate 125 respectively. The presence of a positive logic signal on one input terminal of logic AND gate 124 and one input terminal of logic AND gate 125 results in the clock signal being applied to the output terminal of logic AND gates 124 and 125, respectively. The logic AND gate 124 applies a clock signal to the core processing unit 12 while the logic AND gate 125 applies a clock signal to the remainder of the digital signal processor. The positive signals at the output of the latch units 122 and 123 are the result of an application of control signals to the set input terminal of the latch units. The external control signal indicates that need for the processing activity (and hence the application of the clock signal) by at least portion of the digital signal processor 10. For example, when signal groups are applied to the serial port 18 of the digital signal processor, the serial port 18 and the core processing unit 12 be activated if these components are in an IDLE mode. Consequently, the application of signal groups to the serial port 18 results in an external control signal being applied to both latch unit 122 of the clock control unit 121. Once the external control signal has been applied, the out put signals of the latch units 123 and 124 are set and the clock signals will continue to be distributed throughout the portions of the digital signal processor 10. Within the core processing unit 12, software algorithms determine when an IDLE signal should be generated. For example, when the core processing unit has not been active for a predetermined period of time, a time-out register can generate an IDLE signal that is applied to the clear terminal of latch unit 122. The IDLE signal applied to the clear terminal of the latch unit 122 will remove the positive signal from the output terminal of the latch unit 122 and prevent the clock signal from being transmitted by the clock unit. The clock signal that is applied to the direct memory interface controller 14 by logic AND gate 125 is generated in a similar manner.
As will be clear to those familiar with digital signal processing units, the foregoing is a very general description of the apparatus for providing a IDLE mode of operation and for providing a wake-up signal returning to the active mode. The implementation of IDLE mode can be more complex. For example, particular components, such as the memory unit can be placed independently placed in an IDLE mode.
Recently, a digital signal processing unit with a plurality of (independently operating) digital signal processors has be provided with apparatus that permits the transfer of signal groups for one digital signal processor to a second digital signal processor without the signal groups leaving the digital signal processing unit (cf. APPARATUS AND METHOD FOR THE TRANSFER OF SIGNAL GROUPS BETWEEN DIGITAL SIGNAL PROCESSORS IN A DIGITAL SIGNAL PROCESSING UNIT cited above). With this capability, the possibility can arise that one of the digital signal processors (which are operating independently) involved in the signal group transfer will either be in an IDLE mode or will enter an IDLE mode during the transfer. Either situation can result in an inefficient signal group transfer or in a incorrect signal transfer. The digital signal processors could be constantly maintained in an ACTIVE mode to prevent problems in the processor-to-processor transfer of signal groups, but such a solution would not be energy efficient.
A need has therefore been felt for apparatus and an associated method having the feature that the power consumption in a digital signal processing unit having a plurality of digital signal processors can be reduced while permitting the exchange of signal groups between the digital signal processors in an uninterrupted manner. It would be further feature of the apparatus and associated method that the digital signal processor requiring the signal groups stored in the other digital signal processor can insure that the digital signal processor storing the requisite signal groups is not in the IDLE mode. Similarly, it would be a still further feature of the present invention to insure that neither digital signal processor entered an IDLE mode during the transfer of the signal groups.
The aforementioned and other features can be accomplished, according to the present invention, by providing each digital signal processor of a digital signal processing unit with apparatus for generating a clock-on control signal. Each digital signal processor is provided with apparatus for insuring that a digital signal processor receiving the clock-on signal is not in an IDLE mode of operation. Conducting paths are provided between the digital signal processors to permit one digital processor to wake-up (i.e., change from an IDLE mode to an ACTIVE mode of operation) a second processor. The present invention finds applicability in a digital signal processor-to-digital signal processor transfer of signal groups wherein the digital signal processor having the signal groups required by the second digital signal processor is in the IDLE mode when stored signal groups are needed.